1. Field of the Invention
The present invention relates to layout of a semiconductor storage device, and more particularly, to layout of a semiconductor storage device such as DRAM where a plurality of pair transistors is arranged repeatedly and densely in a sense amplifier.
2. Related Art
For example, DRAM that is a semiconductor storage device has sense amplifiers each of which detects potentials of a pair of bit lines to amplify a minute potential difference therebetween. The function of the sense amplifier is implemented by a pair of MOS (PMOS or NMOS) transistors (hereinafter, referred to as pair transistors). In other words, as shown in FIG. 8, it is necessary to configure a sense amplifier circuit using PMOS pair transistors T1 and T3 and NMOS pair transistors T2 and T4. In FIG. 8, with respect to a minute potential difference between a pair of bit lines BLT and BLN, it is assumed that one bit line BLT is at a relatively high potential. In this case, the NMOS transistor T4 is turned on by the bit line BLT connected to the gate, thereby pulling down the other bit line BLN connected to the drain to the ground potential. The bit line BLN at the ground potential turns on the PMOS transistor T1, thereby pulling up the bit line BLT to the power supply potential. When the bit lines BLT and BLN are in the inverse potential relationship, the operation inverse to the foregoing is carried out. According to the aforementioned operation, the sense amplifier amplifies the potential difference between a pair of bit lines BLT and BLN.
It is necessary to arrange a large number of sense amplifiers repeatedly on a chip corresponding to the number of bit lines, and therefore, the sense amplifiers have extremely significant effects on the chip size of DRAM. FIG. 9 shows a schematic layout diagram of the entire chip. The whole of DRAM is comprised of, for example, four banks 10, and a peripheral circuit area 11 is provided between the banks 10. In FIG. 9, the vertical direction is a direction in which the bit lines extend (hereinafter, referred to as a bit line direction), while the horizontal direction is a direction perpendicular to the bit line direction (hereinafter, referred to as a bit line perpendicular direction). Each of the banks 10 is divided into a plurality of memory cell areas 12 including a predetermined number of word lines and a predetermined number of bit lines.
On the lower side of FIG. 9 is shown an enlarged view of the memory cell area 12 and its surroundings. Around the memory cell area 12 are disposed a word driver area 13 that drives the word lines, and a sense amplifier area 14 comprised of the above-mentioned sense amplifiers. The sense amplifier area 14 thus needs to be provided as a division for each memory area 12, and therefore, has a considerable effect on the chip size. Accordingly, it is required to design the sense amplifier particularly in a small size among circuits constituting DRAM.
Further, considering the function of the sense amplifier as described above, since the minute potential difference to amplify corresponds to extremely small electric charge to be stored in a memory cell, in order to perform appropriate amplification, a pair of bit lines also require a design with balanced loads such as resistance and capacitance. When the resistance and capacitance of a pair of bit lines is not suitable, serious failures may occur such as inversion of data to store, and therefore, such a design is important that a pair of bit lines keep excellent balance therebetween.
As described above, in the design of a sense amplifier, the issue is a design in consideration of both improvements in characteristics and reduction in area. Constitution examples of the sense amplifier based on such an issue have conventionally been proposed. For example, one of the conventional constitution examples (see FIG. 6 in JP H11-307741) or another one of the conventional constitution examples (see FIG. 8 in JP 2000-22108) discloses a constitution such that two pair transistors in line, i.e. four transistors are arranged in the bit line direction in an area of a pair of bit lines, and that such a layout is repeated as a repetition unit according to a pitch of the bit lines. These constitutions of a sense amplifier are obtained by devising a layout in consideration of both effects of the improvements in characteristics and reduction in area.
However, according to reduction in memory cell size with progress of manufacturing techniques, the bit line pitch dependent on the memory cell size has been narrowed. In forming a transistor in a group of pair transistors as described above, considering physically providing the gate, drain/source diffusion layer, contact and the like, arrangements corresponding to narrowed bit line pitches have become difficult gradually.
For example, FIG. 10 is a view showing a layout of a group of pair transistors according to the conventional arrangement. In FIG. 10, eight transistors T1 to T8 constitute pair transistors T1 and T2, pair transistors T3 and T4, pair transistors T5 and T6, and pair transistors T7 and T8. A pair of bit lines (BL1T, BL1N and the like) is arranged for each pair of transistors. In the bit line perpendicular direction (horizontal direction as viewed in the figure) of the four pair transistors are formed a diffusion layer 201, each gate 202 in the shape of a ring, drain (diffusion layer) 203, source (diffusion layer) 204, wiring 205, upper wiring 206, contact 207 and through hole 208. With consideration given to the bit line pitch and required function elements, the layout provides a high dense arrangement under the most extreme conditions. If structural elements are configured with a bit line pitch narrower than the limit in FIG. 10, such a pitch becomes a factor to cause a short-circuit of different contacts in manufacturing. Further, decreasing the width and size of a structural element of a layout becomes factors of a break in wiring or blockage of the contact. Accordingly, it is difficult to make pair transistors finer in the configuration as shown in FIG. 10.
Meanwhile, FIG. 11 is a view showing a layout of a group of pair transistors provided with measures as described above. In FIG. 11, the same circuit as in FIG. 10 is comprised of a different layout, while combinations of four pairs are the same as in FIG. 10, i.e. pair transistors T1 and T2, pair transistors T3 and T4, pair transistors T5 and T6, and pair transistors T7 and T8 exist. In FIG. 11, with respect to four pairs of pair transistors for a pair of bit lines, the pair transistors are arranged in two stages in the bit line perpendicular direction, while being arranged also in two stages in the bit line direction. In this respect, the layout in FIG. 11 is different from that in FIG. 10. Such a constitution provides the pair transistors with the same combinations as in FIG. 10, while shifting the arrangement, eases physical limits such as wiring in the horizontal direction, intervals and the like in consideration of improvements in characteristics, and thus is an advantageous constitution in reduction in bit line pitch.
However, even when the constitution as shown in FIG. 11 is adopted, since the pair transistors have a two-stage structure in the bit line direction, it is inevitable that the size in the bit line direction is extremely increased as compared to the constitution of FIG. 10. In other words, the constitution of FIG. 11 still has the problem of having a significant effect on the chip size.